1. Field of Invention
The present invention relates to a type of package structure suitable for surface mount technology. More particularly, the present invention relates to a type of package structure whose lead frame leads are not directly protrudent to the outside. Furthermore, the leads are positioned alternately so that the external connection points are distributed further apart.
2. Description of Related Art
Integrated circuits (ICs) are so common that they are used in every aspect of our lives. However, to fabricate an IC, hundreds of steps have to be taken over a period of one to two months. Fundamentally, the IC industry involves four major branches including IC design, wafer fabrication, wafer testing and wafer packaging. To maintain the IC industry, requires investment of research capital and constant development of advanced technologies. Therefore, the IC industry is a high-risk business.
In general, IC production can be subdivided into three stages, namely, the silicon wafer fabrication stage, the integrated circuit fabrication stage and the IC chip packaging stage. The packaging of the IC chip is really the last step in the fabrication of an integrated circuit product. From years of packaging practices, the packaging method and external appearance have mostly been standardized.
Due to rapid development in integrated circuit technology, conventional packaging methodology using a lead frame, for example, the dual inline package (DIP), is unable to meet the demands of more advanced processing methods. At present, most semiconductor manufacturers are utilizing surface mount technology (SMT) in their fabrication. Surface mount technique is able not only to eliminate drilling of lots of holes in the circuit board, but is also capable of reducing the lead pitch between the metallic leads when the lead frame is packed into a package having, for example, gull wing leads or J-leads. In view of the convenience of using surface mount technologies, the following discussion is based on surface mount IC fabrication method.
For example, the conventional method of packaging a lead frame into a package having gull wing leads is illustrated in FIGS. 1A and 1B below. FIG. 1A and FIG. 1B are the respective side view and top view of a conventional IC package having gull wing leads. In FIGS. 1A and 1B, a package can be divided into a plastic body 10 and external metal leads 11. As shown in FIG. 1B, the distance, separating one lead from its neighbor, called lead pitch 12, cannot be too small. If lead pitch 12 is too small, short-circuiting of neighboring leads 11 can easily occur when the subsequent surface mount operation is carried out, thereby leading to a drop in the yield.
In addition, conventional lead frame is packaged using a dual side molding process. Therefore, the metallic leads 11 protrude from the plastic body 10, and the package is connected with the IC board by the portions of the metal leads protruding from the plastic body. If the metallic leads are not properly handled, the leads may be bent. Hence, the yield from the surface mount operation is lowered.
Another conventional packaging method is the grid array packaging method. In this method, connection between the IC board and the package is through the underside of the plastic body. The contact points layout of the conventional grid array package is column type. Although the problem of bent leads is solved by this type of arrangement, its column grid array structure makes it difficult to implement further reduction of distance between neighboring contact points without causing short-circuiting. Hence, the yield of this packaging method is still low.
In summary, defects in the conventional method of packaging include:
(1) As the distance separating neighboring leads is reduced, short-circuiting between neighboring leads easily occurs after the package is attached to an IC board using a surface mount technique. Hence, the overall yield of the process is low.
(2) Because the method of attaching the package onto an IC board is through metal leads protruding from a plastic body, the metal leads can be bent when the package is improperly handled. This will contribute to failure in lead attachment after going through a surface mount operation.
In light of the foregoing, there is a need to provide a better method of packaging an IC chip that can produce a higher yield rate using surface mount technology.
Accordingly, the present invention is to provide an interlace grid array package structure and method of manufacture that can increase the pitch of neighboring contact points so that short-circuiting between neighboring leads is greatly reduced after attachment of the package to an IC board using a surface mount technique, thereby increasing the product yield.
In another aspect, this invention is to provide an interlace grid array package structure whose connection with an IC board is through the underside of the plastic body. Hence, the metal leads of lead frame are not exposed, thereby avoiding the problem of bent leads and reducing overall packaging area and thickness.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing an interlace grid array package. The method comprises the steps of first providing a lead frame and an interlace grid array tape, where the lead frame at least includes a die paddle and a plurality of leads, and where the interlace grid array tape has a plurality of holes formed thereon. Next, the interlace grid array tape is attached to one side of the lead frame, wherein each hole on the interlace grid array tape is matched in position against a corresponding lead of the lead frame. Subsequently, die attach, wire bonding and molding processes are sequentially carried out on the other side of the lead frame. The interlace grid array packaging method provided by this invention also permits the die attach, wire bonding and molding processes to be performed on one side of the lead frame first, before attaching the interlace grid array tape on the other side of the lead frame.
In yet another aspect, this invention provides an interlace grid array package structure comprising the following: a lead frame having a first side and a second side, the lead frame also including a die paddle and a plurality of leads; a silicon chip located above the die paddle on the first side of the lead frame, with the silicon chip electrically connected to the lead frame; a packaging material for enclosing the silicon chip and the first side of the lead frame; and an interlace grid array tape having a plurality of holes arranged alternately, whose positions correspond to the leads of the lead frame.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.